Semiconductor Manufacturing Final Test Yield Optimization and Wafer Acceptance Test Parameter Inverse Design Using Multi-Objective Optimization Algorithms

Dan Jiang

doi:10.1109/ACCESS.2021.3117576

2021-01-01

DOI：10.1109/ACCESS.2021.3117576

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摘要

En 中文

In the semiconductor industry, many previous optimization studies have been carried out at the integrated circuit front-end design phase to identify optimal circuit elements' size and design parameters. With the scaling of device dimensions, semiconductor manufacturing back-end Final Test (FT) yield is increasingly influenced by systematic or random process variations. As a result, the FT yield is not fully guaranteed by design phase optimization due to existing limitations of yield simulation models and coverage. Very few studies have attempted to incorporate the production FT yield data into process variation optimization and inverse design. In this paper, we introduce a novel framework for FT yield optimization and Wafer Acceptance Test (WAT) parameter inverse design using multi-objective optimization algorithms. This provides a solution to monitor and quickly adjust process variations to maximize FT yield without expensive characterization or design correction after products are released into the production phase. Both yield optimization and process shift feasibility are to be taken into consideration by formulating these factors into a two objective optimization problem. One objective is to minimize FT yield loss, wherein the yield loss is predicted by a machine learning model. The other objective is to minimize the total WAT parameters shift distance from the current standard setting. Three widely used multi-objective algorithms NSGA-II, SMPSO and GDE3 are applied, compared and discussed. An automatic parameter tuning approach using Sequential Model-based Algorithm Configuration (SMAC) and entropy-based termination criterion is applied to reduce the execution time whilst maintaining the optimization algorithms' performance. Real production data for CMOS 55nm chip are used to validate the framework and the results point to the effectiveness of yield improvement and accurate identification of the optimal WAT parameter combination.

Keyword:

Optimization

Production

Manufacturing

Semiconductor device modeling

Prediction algorithms

Fabrication

Biological system modeling

Semiconductor manufacturing

yield prediction

inverse design

final test

multi-objective optimization

smart manufacturing

process variation

期刊

IEEE Access

IF:

3.6

论文数:

9.8W

被引数:

29.4W

机构

silicon laboratories, inc.

学者数:

论文数: 18

被引数: 0

singapore university of technology & design

学者数:

2.8K

论文数: 3.6K

被引数: 5

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