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Simplified and Efficient 2-D DWT Hardware Design for Visual Sensor
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DOI：10.1109/JSEN.2025.3533890.png)
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摘要
En 中文
In this article, a simplified efficient 2-D discrete wavelet transform (DWT) architecture based on the lifting scheme is presented. By approximating the multipliers required for the multiplication operations in the Cohen-Daubechies-Feauveau (CDF) 9/7 filter, computational resources are significantly reduced. In addition, the strip-based scanning method requires minimal storage resources; for single-level 2-D DWT, there is no need for RAM resources that are dependent on image size. This characteristic makes the proposed architecture particularly well-suited for applications in wireless visual sensor networks (WVSNs). The proposed 2-D DWT and IDWT hardware implementations ensure a reconstructed quality exceeding 90.56-dB peak signal-to-noise ratio (PSNR) for various N x N images with low power consumption. Compared to existing 2-D DWT architectures, our design offers significant advantages, particularly when processing larger block sizes. The area-delay product (ADP) is reduced by at least 10.02%, the energy per image (EPI) decreases by 75.98%, and power consumption is lowered by 53.52%. Furthermore, the circuit performance in the multilevel architecture is outstanding, and the savings in required resources and energy make the proposed architecture highly suitable for applications in WVSNs.
Keyword:
Discrete wavelet transforms
Adders
Computer architecture
Sensors
Hardware
Wireless sensor networks
Visualization
Parallel processing
Wireless communication
Strips
2-D discrete wavelet transform (DWT)
hardware design
lifting architecture
very-large-scale integration (VLSI)
visual sensor
