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SOM accelerator system
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DOI：10.1016/S0925-2312(98)00042-3.png)
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摘要
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Many applications of self-organizing maps (SOM) require high computing performance in order to be efficient. Because of the regular and modular structure of SOMs, a custom hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this article a high-performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit (ES2 1.0 mu m CMOS) contains 25 processing elements in a 5 x 5 array. Due to the scalability of the chips a VMEbus board was built with 16 ICs on it. The controllers for the VMEbus and the SOM hardware are realized using FPGAs. The system runs SOM applications with up to 400 elements in parallel mode (20 x 20 map). Each model vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning). It is integrated in a simulation framework for neural networks, that contains software tools for self-organizing maps as well as for neural associative memories, tools for pre- and postprocessing and tools for graphical analysis of the simulation results. (C) 1998 Elsevier Science B.V. All rights reserved.
Keyword:
neural hardware system
self-organizing maps
hardware accelerator
VLSI-design
期刊
IF:
6.5
论文数:
2.5W
被引数:
6.5W
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