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Sparse Compressed Spiking Neural Network Accelerator for Object Detection
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DOI：10.1109/TCSI.2022.3149006.png)
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摘要
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Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because SNNs contain extra time dimension information, the SNN accelerator will require more buffers and take longer to infer, especially for the more difficult high-resolution object detection task. As a result, this paper proposes a sparse compressed spiking neural network accelerator that takes advantage of the high sparsity of activation maps and weights by utilizing the proposed gated one-to-all product for low power and highly parallel model execution. The experimental result of the neural network shows 71.5% mAP with mixed (1,3) time steps on the IVS 3cls dataset. The accelerator with the TSMC 28nm CMOS process can achieve 1024x576.29 frames per second processing when running at 500MHz with 35.88TOPS/W energy efficiency and 1.05mJ energy consumption per frame.
Keyword:
Object detection
Hardware
Convolution
Training
Neurons
Parallel processing
Topology
Spiking neural network
computer vision
object detection
VLSI hardware design
期刊
IF:
5.2
论文数:
9.8K
被引数:
2.2W
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