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Stacked-Switch Power Factor Correction Architecture
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DOI：10.1109/TPEL.2023.3244538.png)
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摘要
En 中文
Two-stage power factor correction (PFC) architecture, consisting of a boost PFC front end and an isolated dc- dc converter, is widely used in ac-dc applications. However, the boost PFC front end loses zero-voltage-switching (ZVS) under high-line conditions, limiting its practical switching frequency. Consequently, a relatively large boost inductor and electromagnetic interference (EMI) filters are needed in the two-stage architecture, leading to a lower power density design. This article proposes a stacked-switch PFC architecture that allows all switches to achieve full-load-range ZVS at a universal input while reducing the component counts compared to the two-stage architecture. As a result, the stacked-switch architecture can operate efficiently at a much higher switching frequency than the two-stage architecture, allowing for higher power density and lower cost. Additionally, this architecture can be operated at a constant switching frequency, which is beneficial for simplifying the magnetics and controller design. A 150-W-universal-input prototype is built to verify the effectiveness of the stacked-switch PFC concept. The prototype measures 92.9% peak efficiency and 53.9-W/in(3) power density by box volume.
Keyword:
Zero voltage switching
Density measurement
Switching frequency
Switches
Power system measurements
Transformers
Electromagnetic interference
AC/DC
active decoupling
GaN
power factor
power factor correction (PFC)
single phase
soft switching
wide band-gap
zero-voltage switching (ZVS)
期刊
IF:
6.5
论文数:
1.7W
被引数:
8.3W
机构
引用论文
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