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Time-Interleaved ΣΔ Modulators for FPGAs
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DOI：10.1109/TCSII.2014.2345293.png)
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摘要
En 中文
This brief describes and analyzes a technique of increasing a sampling rate in a sigma-delta (Sigma Delta) modulator based on a discrete-time description, which is an extension of existing techniques of parallelization. The limitations in the signal-to-noise ratio and the maximum increase of the sampling rate in a digital system are explained, and a structure of a low-pass S. modulator characterized by a short critical path is used in this brief to validate the technique. An implementation of a modulator shows the increase in the sampling rate from 100 to 400 MHz.
Keyword:
Sampling frequency
sigma-delta (Sigma Delta)
time interleaved (TI)
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