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Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs

delete2020-10-01
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PRE
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A
Armia Salib *
M
Mark F. Flanagan
B
Barry Cardiff
DOI:10.1109/TCSII.2019.2956101delete
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摘要

摘要

En 中文
This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can provide an improvement in the SFDR without incurring a penalty in the SNDR. The calibration algorithm places some constraints on the random sampling sequence, which are satisfied via a proposed sequence generation algorithm based on a linear-feedback shift register (LFSR). We also show how the timing reference can be selected so as to reduce the requirements of the time-skew correction circuit, and we demonstrate the resulting production yield improvements. The proposed algorithm was synthesized for a TIADC composed of 9 sub-ADCs having an aggregated sampling rate of 2.4GS/sec in a 28nm process; the design occupies 0.014mm(2) and consumes 2.93mW. We demonstrate that the proposed algorithm successfully compensates the time-skew mismatch, allowing to achieve SFDR above 100dB.
Keyword:
Calibration
Timing
Estimation
Correlation
Circuits and systems
Degradation
Convergence
Time-skew
TIADC
background calibration
blind estimation
random sampling sequence
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期刊

I
IEEE Transactions on Circuits and Systems and Express Briefs
IF:
4.9
论文数:
8.8K
被引数:
2.5W

机构

U
university college dublin
学者数:
2.6W
论文数: 2.2W
被引数: 22
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