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TinyJAMBU Hardware Implementation for Low Power
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DOI：10.1109/ACCESS.2024.3438378.png)
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In this paper, we present hardware implementations of the lightweight TinyJAMBU cipher with reduced power consumption using a mechanism based on shift register parallelization. The power consumption in digital circuits depends linearly on the switching activity of the logic gates. The parallelization technique reduces the number of switches per clock cycle of the shift registers, which can significantly reduce power consumption. This technique has been applied to the TinyJAMBU cipher, a finalist in the NIST lightweight cryptography standardization process with the lowest resource and power consumption. The implementations we present use the logical parallelization technique in the cipher's NLFSR, which is the basic block of TinyJAMBU, and in the key register. Measurements with data from various post-place and route simulations, performed for the Xilinx 7-Series family of FPGAs, are presented to demonstrate the effectiveness of the proposed technique in reducing power consumption, achieving a reduction of more than 30% in dynamic power consumption compared to the standard implementation, with almost no increase in resource consumption. Therefore, the ciphers hardware implementations proposed in this paper are highly suitable for use as hardware peripherals in applications with severe constraints on available resources and power, such as low-power microcontrollers that are widely used in the IoT field.
Keyword:
Power demand
Shift registers
Ciphers
NIST
Hardware
Nonce
Standards
AEAD
lightweight cryptography
TinyJAMBU
期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
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