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Total ionizing dose effect modeling method for CMOS digital-integrated circuit
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DOI：10.1007/s41365-024-01378-5.png)
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Simulating the total ionizing dose (TID) of an electrical system using transistor-level models can be difficult and expensive, particularly for digital-integrated circuits (ICs). In this study, a method for modeling TID effects in complementary metal-oxide semiconductor (CMOS) digital ICs based on the input/output buffer information specification (IBIS) was proposed. The digital IC was first divided into three parts based on its internal structure: the input buffer, output buffer, and functional area. Each of these three parts was separately modeled. Using the IBIS model, the transistor V-I characteristic curves of the buffers were processed, and the physical parameters were extracted and modeled using VHDL-AMS. In the functional area, logic functions were modeled in VHDL according to the data sheet. A golden digital IC model was developed by combining the input buffer, output buffer, and functional area models. Furthermore, the golden ratio was reconstructed based on TID experimental data, enabling the assessment of TID effects on the threshold voltage, carrier mobility, and time series of the digital IC. TID experiments were conducted using a CMOS non-inverting multiplexer, NC7SZ157, and the results were compared with the simulation results, which showed that the relative errors were less than 2% at each dose point. This confirms the practicality and accuracy of the proposed modeling method. The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID, which has potential applications in the design of radiation-hardening tolerance in digital ICs.
Keyword:
CMOS digital-integrated circuit
Total ionizing dose
IBIS model
Behavior-physical hybrid model
Physical parameters
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3.8
论文数:
2.2K
被引数:
3.4K
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