Trident: The Acceleration Architecture for High-Performance Private Set Intersection

doi:10.1109/TC.2024.3517738

Trident: The Acceleration Architecture for High-Performance Private Set Intersection

2024-01-01

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DOI：10.1109/TC.2024.3517738

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Private Set Intersection (PSI) is imperative in discovering the properties of the same data owned by two competitive parties, without revealing anything else of their respective data asset. Existing PSI solutions such as APSI and ORI-PSI suffer from severe communication and computation overhead due to inefficient communication and FHE polynomial evaluation, which hinders their deployment in practice. This issue is evident in both the upper-level protocol and the lower-level hardware platform. In this paper, we propose a novel software/hardware co-design acceleration architecture for PSI, termed as Trident, which includes two tightly coupled segments: from the protocol perspective, we investigate existing bottlenecks and propose a new PSI protocol with significantly less communication and computation under the security guarantee; besides, we re-architect the hardware platform by designing a PSI-specific accelerator, implemented with both FPGA and ASIC, targeting the key operations in the proposed protocol. We build a real-world experimental environment with two instantiated parties to verify the acceleration architecture, and highlight the following results: (1) up to 130x/145x speedup for the computation of receiver and sender parties; (2) up to 37x reduction of communication overhead. (3) up to 93,651x and 74,326x higher energy efficiency over the CPU-based ORI-PSI and APSI, respectively.

Keyword:

Protocols

Receivers

Cryptography

Hardware

Central Processing Unit

Random access memory

Data privacy

Polynomials

Field programmable gate arrays

Computer architecture

Private set intersection (PSI)

fully homomorphic encryption (FHE)

FPGA accelerator

privacy computing

Trident: The Acceleration Architecture for High-Performance Private Set Intersection

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