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Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors - Chip design and system implementation
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DOI：10.1109/2944.778326.png)
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We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry, This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.
Keyword:
cellular logic arrays
CMOS integrated circuits
integrated optoelectronics
optical interconnections
smart pixels
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