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Ultra-high performance, low-power, data parallel radar implementations
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DOI：10.1109/MAES.2006.1626056.png)
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摘要
En 中文
Radar involves similar operations applied to large amounts of data. It is thus well suited to data parallel (SIMD) hardware. In the past, large data-parallel machines have been applied to radar with limited success. This has been due to such reasons as programming issues, cost, and the hardware being too big for most embedded applications. Most SIMD machines went away a decade ago. There is now a new generation of SIMD COTS technology with powerful Processing Elements (PEs) and floating-point hardware. WorldScape is applying these chips to radar processing, and has demonstrated significantly more performance with much lower power dissipation (GFLOPS/Watt). These implementations provide attractive alternatives to traditional FPGA and DSP solutions. Lockheed-Martin has provided benchmark validation testing and support for these implementations. The current implementation is based on a 64 PE, 25 GFLOP CS-301 chip supplied by ClearSpeed Technology PLC. WorldScape has demonstrated FFT, Pulse Compression, a form of QR factorization, and other applications on this generation of hardware using a mix of C-level programming and optimized assembly. The next generation chip is compatible, but also has several improvements that will significantly enhance I/O performance as well as raw GFLOP throughput. An updated demonstration and discussion of a Scalable Processing Platform for embedded radar processing which significantly improves I/O performance and provides a roadmap to government-qualified hardware for technology insertion. Architectures, data parallel coding approaches, additional functionality of the Scalable Processing Platform, and relevance to embedded defense radar applications will be discussed.
