Vertically Integrated Multiple Nanowire Field Effect Transistor

doi:10.1021/acs.nanolett.5b03460

Vertically Integrated Multiple Nanowire Field Effect Transistor

2015-11-11

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DOI：10.1021/acs.nanolett.5b03460

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Abstract

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A vertically integrated multiple channel-based field-effect transistor (PET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Keywords:

silicon nanowire (SiNW)

gate-all-around (GAA)

vertical integration

field-effect transistor (FET)

three-dimensional nonvolatile memory

one-route all-dry etch

Vertically Integrated Multiple Nanowire Field Effect Transistor

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