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VLSI circuit performance optimization by geometric programming
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DOI：10.1023/A:1013345330079.png)
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Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem considering delay, chip area and power dissipation can be reduced to unary geometric programs. We present a greedy algorithm to solve unary geometric programs optimally and efficiently. When applied to VLSI circuit component sizing, we prove that the runtime of the greedy algorithm is linear to the number of components in the circuit. In practice, we demonstrate that our unary-geometric-pro gram based approach for circuit sizing is hundreds of times or more faster than other approaches.
Keyword:
VLSI design
unary geometric programming
circuit performance optimization
transistor sizing
gate sizing
wire sizing
Lagrangian relaxation
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