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VLSI placement and area optimization using a genetic algorithm to breed normalized postfix expressions
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DOI：10.1109/TEVC.2002.802872.png)
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摘要
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We present a genetic algorithm (GA) that uses a tree construction process for the placement and area of soft modules in very large scale integration floorplan We have overcome the serious representational problems associated with encoding slicing floorplans into GAs and obtained excellent (often optimal) results for module sets with up to 100 rectangles. The slicing tree construction process by our GA to generate the floorplans has a runtime scaling O (n l g n). This compares very favorably with other recent approaches based on nonslicing floorplans that require much runtimes. We demonstrate that our GA outperforms a simulated annealing implementation with the same representation and mutation operators as the GA.
Keyword:
floorplanning
genetic algorithm
normalized postfix expression
simulated annealing
slicing tree
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