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98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR
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DOI：10.1109/TCSII.2025.3552742.png)
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Abstract
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This brief presents a novel multi-residue two-step incremental ADC (IADC) with a two-capacitor SAR. It introduces the multi-residue sampling (MRS) technique to enhance Signal-to-Quantization-Noise Ratio (SQNR) and to minimize the thermal noise penalty commonly occurring in high-resolution IADCs. The multi-residue incremental ADC (MRIADC) was designed in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu $ </tex-math></inline-formula>m CMOS process. It achieves an SNDR of 98 dB over a 2.4 kHz signal band. The power consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$78.76~\mu $ </tex-math></inline-formula>W from a 1.8 V supply voltage which gives Schreier Figure of Merit of 172.9 dB.
Keywords:
Analog-to-digital converter
incremental data converters
multi-residue two-step incremental ADC
multi-step incremental ADC
SAR ADC
noise-shaping SAR
delta-sigma IADC
noise shaping (NS)
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