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A 13-bit 70-MS/s SAR-Assisted Cyclic ADC With Charge-Reused 2-bit/Cycle Operation
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DOI：10.1109/tcsi.2026.3690163.png)
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Abstract
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This article presents an energy-efficient 13-bit high-speed SAR-assisted cyclic ADC. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1^{\text {st}}$ </tex-math></inline-formula> stage 6-bit SAR ADC coarsely quantizes the input signal. The proposed charge-reused 2-bit/cycle cyclic ADC doubles the conversion speed with 50% reduction in capacitor number. Owing to the comparator noise suppression circuit and mismatch robustness of the cyclic ADC, an interstage gain of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> is required, which significantly relaxes the amplifier design and improves its total harmonic distortion (THD). Fabricated in 40nm 1P8M CMOS, the proposed SAR-assisted cyclic ADC achieves 13b resolution with SNDR and SFDR of 66.5dB and 80.1dB, respectively, with a Nyquist-rate input at 70MS/s without calibration while consuming 0.88mW power, yielding FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> and FoM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> of 175dB and 6.9fJ/conv., respectively. The ADC demonstrates a sub-1dB SNDR variation across the measured 9 chips, presenting the robustness against variations.
Keywords:
Analog-to-digital converter (ADC)
adaptive conversion cycle
cyclic ADC
energy-efficient ADC
low capacitor mismatch
offset cancellation
SAR-assisted ADC
2-bit/cycle operation
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