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A 2T1MTJ-Based In-Memory Computing Macro With Time-Domain Accumulation and Ramp-Type Readout
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DOI：10.1109/TCSII.2025.3615803.png)
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Abstract
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This brief presents an area-efficient 28 nm computing-in-memory (CIM) macro that utilizes a 2T1MTJ array to perform robust and efficient time-domain computations. To overcome the challenges of MRAM-based CIM in which the limited On/Off ratio causes large errors in conventional current or charge-summation based CIM schemes, we propose a time-domain accumulation scheme featuring an odd/even complementary computation to balance the load of bit lines and a dual-edge (rising/falling) computation method that doubles throughput. A ramp-based readout scheme, which employs a shared, high-linearity, ring-based Time-to-Digital Converter (TDC) with PVT-tracking replica cells, improves both storage density and power efficiency. Evaluated in 28 nm CMOS technology, the macro demonstrates superior MAC linearity, achieving an energy efficiency of 427.6 TOPS/W at 0.6V and an area throughput of 5.03 TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With a classification accuracy of 92.75% on the CIFAR-10 dataset, this approach also achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.8\times $ </tex-math></inline-formula> increase in storage density, compared with state-of-the-art MRAM-based CIM.
Keywords:
Computing-in-memory (CIM)
MRAM
time-domain computing
ramp readout
time-to-digital converter (TDC)
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