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A 4x4 modified 8 T SRAM cell array using power gating technique
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DOI：10.1016/j.matpr.2020.08.746.png)
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Abstract
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Low power chip design is focused due to increase in demand of portable battery devices which is involved in day to day life. The memory plays an important role in all silicon on chip devices. SRAM's are most widely used memory in the VLSI devices due to it's better performance compared to DRAM. In Recent years SRAM, plays a dominant part in chip design and becomes the crucial research due to the high demand by the use of battery operated devices. To make the circuit more efficient the design should be successively operated with low leakage power at sub-threshold regions. A modified 8 T SRAM cell is designed and simulated using Tanner 13.1 EDA tool. (c) 2021 Elsevier Ltd. All rights reserved. Selection and peer-review under responsibility of the scientific committee of the International Conference on Advances in Materials Research-2019.
Keywords:
SRAM
Portable devices
Low leakage power
Battery devices
Performance
Sub threshold
Acknowledgements We thank the authors of referees for their useful suggestions which helped us to proceed further in our research
We also thank our management
Principal Dr
P
Vijayakumar and Head of the Department Dr
P
Krathigaikumar for their support towards the research and guidance all the time
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