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A bit-parallel molybdenum disulfide computer built through multi-level co-optimization
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AI
DOI：10.1038/s41928-026-01641-0.png)
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Abstract
En 中文
The sustainable development of artificial intelligence requires energy-efficient computing technology. Two-dimensional semiconductor digital electronics could potentially provide such capabilities, and promising single devices and small circuits have been developed. However, very large-scale integration remains challenging due to the inability to control atomic-scale defects and mesoscopic device variations, as well as the lack of macroscopic variation-aware design methodology. Here we report a molybdenum disulfide computer that combines a 0.5-μm industrial fabrication process and a back-end-of-line-integrated academia laboratory process. The computer comprises 1,433 transistors interconnected by four metal layers within a compact footprint, offering an integration density of around 9,336 transistors per square millimetre. The computer can store data on-chip in the register file and perform arithmetic operations on multiple-bit data parallelly at a 1-kHz clock frequency. Key to the development of this system is a multi-level co-optimization methodology that spans transistor, standard cell, logic synthesis and interconnect design. By combining a 0.5-μm industrial fabrication process and a back-end-of-line academia laboratory process, as well as using a multi-level co-optimization methodology, a molybdenum disulfide computer can be fabricated that comprises 1,433 transistors interconnected by four metal layers.
Keywords:
molybdenum disulfide
bit-parallel computing
multi-level co-optimization
2D semiconductor
energy-efficient computing
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