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A Booth-Encoded Digital Computing-in-Memory Macro With Configurable Approximate Compressor Tree
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DOI：10.1049/ell2.70434.png)
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Abstract
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The surging demand for large model inference-driven by billions of daily artificial intelligence (AI) interactions-has intensified the need for energy-efficient AI devices. This work presents a configurable Booth-encoded digital computing-in-memory (CIM) macro in 28 nm CMOS, supporting both accurate and approximate INT8 computations to explore a trade-off among accuracy, flexibility, and power, performance, and area (PPA). Its computing array leverages row-shared Booth encoders integrated with dual-bit SRAM storage to generate signed partial products simultaneously across multiple channels to achieve double throughput compared to bit-serial implementations, incurring only 37.5% area overhead. Critically, implementing sign compensation bit pre-processing on these partial products simplifies the subsequent addition, thereby reducing the adder area. The configurable approximate compressor tree reduces power by 23.49% at 500 MHz with an error compensation scheme reducing offset errors in approximate mode. Combined with truncation-aware compensation, the macro achieves 512 GOPS and 35.41 TOPS/W at < 0.28% hardware error without retraining.
Keywords:
Circuits and Systems
CMOS digital integrated circuits
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