A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range

Eunhwan Kim

doi:10.1109/TCSII.2023.3266239

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range

2023-09-01

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DOI：10.1109/TCSII.2023.3266239

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We present a 9T1C SRAM cell-based capacitive computing-in-memory circuit for neural network computation. The proposed design improves tolerance against process variation with a smaller cell area compared to previous capacitive SRAM CIM designs while inheriting the advantage of capacitive SRAM CIM hardware such as the linearity in multiply-accumulate (MAC) results and suppression of the static readout current. We also demonstrate a compact and low-power ADC for CIM readout, which improves the energy efficiency significantly. Finally, we demonstrate a programmable on-chip ADC reference voltage generator circuit for adjusting the ADC input range using bitcell replica arrays. The proposed circuit reduces the ADC bitresolution requirement by considering the distribution of MAC results, and also helps to address the effect of the parasitic bitline capacitance. Measurement results show that a 128x128 macro fabricated in a 28 nm CMOS achieves 1519.5 TOPS/W at 0.7 V.

Keywords:

Random access memory

Voltage

Inverters

Transistors

Computer architecture

Microprocessors

Logic gates

Computing-in-memory

capacitive coupling

neural network

programmable reference voltage

SRAM

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range

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