A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

doi:10.1016/j.compeleceng.2013.11.014

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

2014-01-01

37

PRE

AI

R

R. Garcia

I

Ignacio Algredo‐Badillo

M

Miguel Morales‐Sandoval

C

Claudia Feregrino-Uribe

R

René Cumplido *

DOI：10.1016/j.compeleceng.2013.11.014

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This work reports an efficient and compact FPGA processor for the SHA-256 algorithm. The novel processor architecture is based on a custom datapath that exploits the reusing of modules, having as main component a 4-input Arithmetic-Logic Unit not previously reported. This ALU is designed as a result of studying the type of operations in the SHA algorithm, their execution sequence and the associated dataflow. The processor hardware architecture was modeled in VHDL and implemented in FPGAs. The results obtained from the implementation in a Virtex5 device demonstrate that the proposed design uses fewer resources achieving higher performance and efficiency, outperforming previous approaches in the literature focused on compact designs, saving around 60% FPGA slices with an increased throughput (Mbps) and efficiency (Mbps/Slice). The proposed SHA processor is well suited for applications like Wi-Fi, TMP (Trusted Mobile Platform), and MTM (Mobile Trusted Module), where the data transfer speed is around 50 Mbps. (C) 2013 Elsevier Ltd. All rights reserved.

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A compact FPGA-based processor for the Secure Hash Algorithm SHA-256

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