A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA

Jian Zhang

doi:10.1109/TCSII.2022.3199033

A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA

2022-12-01

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DOI：10.1109/TCSII.2022.3199033

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In this brief, an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed. The proposed architecture can be configured in multiple-spike (MS) mode or single-spike (SS) mode to adapt to different spiking convolution neural network (SCNN) models with either rate coding scheme or temporal coding scheme. A skipped zero kernel step is designed to reduce access neuron membrane potentials in memories. In addition, the proposed design supports two pooling methods for increasing flexibility. The proposed architecture is implemented in a Xilinx Kintex-7 FPGA development board, and two SCNN models with different coding schemes are applied to verify the efficiency of the architecture. For the first SCNN model with rate coding scheme, the proposed architecture achieves a 99 % classification accuracy with 0.46 mJ/classification. For the second SCNN model with temporal coding scheme, the proposed architecture obtains a classification accuracy over 95.4 % with 7.4 uJ/classification. Experimental results demonstrate that the proposed design is adaptable and has a low power consumption overhead.

Keywords:

Spiking convolutional neural network (SCNN)

image classification

configurable network

field programmable gate array (FPGA)

event-driven

A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA

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