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A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask
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DOI：10.1109/OJCAS.2026.3656510.png)
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Abstract
En 中文
This paper presents a via-programmable DNN processor architecture, the Via-Programmable Neuron Array (VPNA), designed for low-NRE and low-power AIoT applications. To enable shared base-chip layouts across diverse workloads, a connectivity-aware design ensures tile-to-tile routing under a column-wise placement rule. A $6{\times }6$ programmable-wire structure supports task-specific data paths, and via-based ternary-weight mapping allows multiple tasks to reuse the same base chip with a single via mask. A unified bit-serial neuron circuit supports convolution and pooling operations under both neuron-serial and neuron-parallel modes, completing the functional implementation required for one-dimensional time-series DNNs. Post-layout evaluations in a 40 nm CMOS process demonstrate sub-milliwatt power consumption and sufficient inference accuracy across representative AIoT tasks, including keyword spotting, ECG arrhythmia detection, and EEG seizure detection. Compared with prior FPGA- and ASIC-based accelerators, the proposed architecture achieves a better trade-off among low power, low NRE cost, and task-level flexibility, highlighting its potential as a scalable foundation for future ultra-low-NRE and field-programmable AIoT processors.
Keywords:
Neurons
Convolution
Logic
Costs
Wires
Arrays
Random access memory
Biomedical monitoring
Accuracy
Metals
Bit-serial
low-NRE
low-power
via-programmable
wearable AIoT
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