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A dynamically tunable memory hierarchy
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DOI：10.1109/TC.2003.1234523.png)
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Abstract
En 中文
The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per-application phase basis using a novel configuration management algorithm. In comparison to a conventional design that is fixed at a single design point targeted to the average application, the dynamically tunable cache and TLB hierarchy can be tailored to the needs of each application phase. The configuration algorithm dynamically detects phase changes and selects a configuration based on the application's ability to tolerate different hit and miss latencies in order to improve the memory energy-delay product. We evaluate the performance and energy consumption of our approach and project the effects of technology scaling trends on our design.
Keywords:
high performance microprocessors
memory hierarchy
reconfigurable architectures
energy and performance of on-chip caches
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3.8
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5.3K
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9.8K
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