A fast neural-network algorithm for VLSI cell placement

Cevdet Aykanat

doi:10.1016/S0893-6080(98)00089-6

A fast neural-network algorithm for VLSI cell placement

1998-12-01

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DOI：10.1016/S0893-6080(98)00089-6

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Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average. (C) 1998 Elsevier Science Ltd. All rights reserved.

Keywords:

VLSI circuit design

cell placement problem

field programmable gate array

mean field annealing

neural-network algorithms

A fast neural-network algorithm for VLSI cell placement

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