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A High Performance, Multi-Bit Output Logic-in-Memory Adder
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DOI：10.1109/TETC.2020.2982951.png)
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Abstract
En 中文
Alternative approaches beyond charge-only-based electronics, and particularly, spin-based non-volatile (VN) devices, show promising potential to overcome power and latency issues. The NV spin-transfer torque magnetic random access memory (STT-MRAM), as one of the NV candidates can provide for the digital world the opportunity of an instant-on/off computing system design. It reduces both static and dynamic power caused mainly by the intrinsic leakage currents and large data traffic delay in CMOS logic circuits thanks to its high endurance, admissible read power consumption, and comparable read latency. In this paper, a novel multi-output logic-in-memory (LiM) adder based on STT-MRAM with monolith scheme is proposed, which can be used to design any multi-output LiM-based circuit. Two well-known schemes based on STT-MRAM, serialization, and carry prediction, selected for comparison along with state-of-the art methods. Due to serious reliability challenge in nanometer scale technology, the robustness of proposed adder is also analyzed in presence of CMOS and magnetic tunnel junction (MTJ) process variation. Finally, using the MTJ compact model, as a core element of STT-MRAM and the 16nm PTM CMOS model functional simulations have been done. Our results show that in the worst case, execution time of proposed method is 2x faster than the best related work, 400 and 250 percent improvement is observed in MTJ write energy and average power consumption respectively, and similar to 4 percent degradation is found in read error rate and comparable area overhead. Adder is considered as a case study because of its highest applicability in the processors and the capability of extension to a multi-output one.
Keywords:
Adders
Switches
Nonvolatile memory
Magnetic tunneling
Power demand
Magnetic fields
Reliability
Non-volatility
logic-in-memory
spin-transfer torque
adder design
variation
bit error rate (BER)
multi-output logic-in-memory
area overhead
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