A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher's Sorting Network

doi:10.1109/TCSI.2020.2973249

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A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher's Sorting Network

2020-06-01

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Seyed Mohammad Reza Shahshahani

Hamid Reza Mahdiani *

DOI：10.1109/TCSI.2020.2973249

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Abstract

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Eigenvalue Decomposition (EVD) and Singular Value Decomposition (SVD) are two crucial transformations in many signal processing applications. The main drawback of these algorithms is their computationally intensive nature which prevents them to be efficiently exploited in high-performance, real-time and mobile applications. By extracting the inherent parallelism of the Jacobi SVD, a new parallel data distribution and access pattern for this algorithm is proposed first. Based on the proposed parallel data distribution, a novel shared-memory architecture is then proposed to support EVD/SVD computation in a high-performance and scalable manner. A new Multistage Interconnection Network based on Batcher's odd-even merge sorting network is developed and exploited in the architecture to preserve its performance and scalability by simultaneously connecting different numbers of processing elements to the system memory hierarchy in a parallel conflict-free manner. The proposed architecture can be configured to compute EVD/SVD of matrices of arbitrary size, with different numbers of processing elements achieving a linear speed-up. The synthesis results in a 90 nm technology show that the system with one, two, and four processing elements achieves a throughput of 1.81, 3.63, and 7.26 million EVD/SVD's per second, respectively with a frequency of 813 MHz for an 8x8 matrix.

Keywords:

Jacobian matrices

Computer architecture

Signal processing algorithms

Principal component analysis

Symmetric matrices

Parallel processing

Scalability

ASIC

Batcher's sorting network

brain-computer interface

independent component analysis

Jacobi EVD

SVD

motor imagery

multi-stage interconnection network

scalability

shared-memory architecture

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