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A High-Resolution Delta-Sigma ADC Using Buffered Dynamic Body-Biased Gate-Bootstrapped Switch in 22nm FD-SOI
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DOI：10.1587/elex.23.20260078.png)
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Abstract
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This paper presents a high-resolution second-order deltasigma (Delta Sigma) ADC in 22nm FD-SOI technology. To overcome the tradeoff between voltage headroom and linearity, a buffered dynamic body-Biased (BDBB) gate-bootstrapped switch is introduced. This structure decouples the input signal from the parasitic body capacitance, effectively suppressing harmonic distortion and minimizing aperture jitter. The modulator employs a cascaded integrator feed-forward (CIFF) architecture with gain-boosted op-amps, achieving a peak signal-tonoise and distortion ratio (SNDR) of 104.9 dB and an effective number of bits (ENOB) of 17.1 bits in a 10kHz bandwidth. A digital decimation filter performs 640x downsampling to provide a 24-bit output. Operating at a 1.2 V supply and 12.8 MS/s sampling rate, the proposed design achieves an spurious-free dynamic range (SFDR) of over 100 dB, making it highly suitable for high-precision signal acquisition.
Keywords:
key Delta-Sigma ADC
Buffered Dynamic Body-Biased
Gate-Bootstrapped Switch
FD-SOI Process
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