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A low-latency asynchronous shift register

delete2004-05-01
delete2
PRE
AI
R
R.P.-K. Chan
O
Oliver C. S. Choy
C
Cheung-Fat Chan
K
Kong‐Pang Pun
DOI：10.1109/TCSII.2004.824051delete
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Abstract

Abstract

En 中文
In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.
Keywords:
asynchronous circuit
D flip-flop
differential cascode voltage switch logic (DCVSL)
latency
shift register
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Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.

Journal

I
IEEE Transactions on Circuits and Systems and Express Briefs
IF:
4.9
Papers:
8.8K
Citations:
2.5W

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