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A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator
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DOI：10.1109/TCSII.2011.2180110.png)
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Abstract
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A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3x (3.5x) and 3.7x (5.8x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7x faster at iso-energy(80 fJ) or 3.3x more energy efficient at iso-delay(200 ps) than existing designs.
Keywords:
Binary comparator
digital arithmetic
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