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A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding
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DOI：10.1109/TCSII.2010.2082970.png)
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Abstract
En 中文
In this brief, we introduce a new iterative decoder implementation called pulsewidth-modulated min-sum (PWM-MS), in which messages are exchanged in a pulsewidth-encoded format. The advantages of this method are low switching activity, very low complexity check nodes, low routing congestion, and excellent energy efficiency. We implement a fully parallel PWM offset MS decoder for a (660, 484) regular (4, 15) low-density parity-check code with 4-bit quantization in 0.13-mu m CMOS, with a core area of 5.76 mm(2) (4.24-mm(2) cell area or 556K equivalent AND gates). In postlayout simulations, this decoder achieves an average information throughput of 5.71 Gb/s and an energy consumption of 65.8 pJ per information bit at a signal-to-noise ratio of 5.5 dB. Our results show a 21% reduction in area, a 0.6-dB improvement in coding gain, and an energy efficiency improvement of 19% over the comparable bit-serial MS decoder architecture. We also demonstrate 3-bit implementations, in which the coding gain is traded off for further improvements in throughput, area, and energy efficiency.
Keywords:
Low-density parity-check (LDPC) codes
low power
low switching activity
min-sum (MS) iterative decoding
pulsewidth modulation (PWM)
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