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A new RISC processor architecture for MPEG-2 decoding

delete2002-02-01
delete3
PRE
AI
K
Keita Yamada
M
Motohiro Kojima
T
Toshihisa Shimizu
F
Fumiaki Sato
T
Tadanori Mizuno
DOI：10.1109/TCE.2002.1010104delete
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Abstract

Abstract

En 中文
Most of the processors for MPEG-2 decoding adopt four-way or more complex architecture to decrease the calculation cycles, but on the other hand the processors for system control need more simple architecture. The architecture of an SOC processor must satisfy both requirements, therefore a two-way RISC processor architecture using a four-multiply-add operation is proposed. Next, a simple IDCT algorithm to decrease the calculation cycles using the four-multiply-add operation is investigated. Also, the data transfer for IDCT is discussed and it is found to be possible to carry out the transfer process in parallel with the calculation. As a result of the evaluation for the total calculation cycle, it is concluded that the two-way RISC processor with a 250MHz clock can be applied to an SOC for MPEG-2 decoding. In other words, it is suitable for SOCs for DTV and DVD.
Keywords:
32-BIT MCU
SYSTEM
JPEG

Journal

IEEE Transactions on Consumer Electronics cover
IEEE Transactions on Consumer Electronics
IF:
10.9
Papers:
5.1K
Citations:
6.8K

Organization

No organization information available