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A Novel Bit-Adjustable Column-Parallel ADC for Scalable Emerging Computing Systems
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DOI：10.1109/TCSII.2025.3606496.png)
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Abstract
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This brief presents a bit-adjustable column-parallel analog-to-digital converter (ADC) as a core component for scalable emerging computing systems, such as computing-in-memory (CIM) and optical computing architecture. A shared multi-reference voltage assist technique is proposed to reduce the area overhead and enhance the shared voltage driving capability for supporting large-scale ADC arrays. The quantization precision can be adjusted from 2-bit to 8-bit to accommodate different precision requirement computing architecture. Additionally, the bit-adjustable strategy is designed to reduce the comparator’s power consumption. The ADC array is fabricated in the TSMC 28nm CMOS process. The proposed column-parallel ADC consumes $332~\mu $ W power when operating at 100MS/s sampling frequency and 8-bit quantization precision. By utilizing the shared multi-reference voltage assist technique, the area overhead is reduced by 58% compared with the traditional successive approximation register (SAR) ADC. When reducing the quantization precision from 8 bits to 2 bits, the power consumption is reduced by 59.1%. Measured results show that the ADC achieves an effective number of bits (ENOB) of 7.06 and a Walden figure of merit (FoMw) of 24.8 fJ/conv.
Keywords:
Scalable emerging computing systems
analog-to-digital converter (ADC)
multi-reference voltage assist technique
wide input range comparator
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