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A Novel Modular Positive-Sequence Synchrophasor Estimation Algorithm for PMUs
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DOI：10.1109/TIM.2016.2637578.png)
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Abstract
En 中文
A novel modular positive-sequence estimation algorithm for phasor measurement units (PMUs) is described in this paper with a focus on the restrictions imposed by the IEEE C37.118.1-2011 standard. The first stage consists in a three-phase demodulator which allows us to separate the positive-sequence from the negative-sequence signal in the frequency domain and to eliminate the zero-sequence signal. The second stage is a prefilter that mitigates noise and interference, thus relaxing the filtering requirements of the following stage. The suitability of a linear-phase FIR filter is shown and a comparison of single and multistage designs is presented. On the third stage, a digital state-space-based extension of a synchronous reference frame-phase-locked loop is used for tracking of amplitude, phase, frequency, and rate of change of frequency. It is shown that a phase predictor inside the loop is required. The fourth stage is a compensation algorithm which takes into account the narrowband nature of the input signal to perform an accurate compensation of the filter effects on the signal of interest. Analytical properties of the system are then presented, providing insight into the main factors that affect global performance. Finally, a strict evaluation of the system is presented for both M and P class PMU.
Keywords:
IEEE standards
linear-phase filters
phase-locked loops (PLLs)
phasor measurement units (PMUs)
system analysis and design
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