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A novel multiplexer-based low-power full adder

delete2004-07-01
delete98
PRE
AI
J
Jiang, YT
A
A. Al-Sheraidah
Y
Yikai Wang
E
Edwin H.‐M. Sha
J
Jin-Gyun Chung
DOI：10.1109/TCSII.2004.831429delete
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Abstract

Abstract

En 中文
The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.
Keywords:
full adder
low power
multiplexer
very large-scale integrated (VLSI) circuit

Journal

I
IEEE Transactions on Circuits and Systems and Express Briefs
IF:
4.9
Papers:
8.8K
Citations:
2.5W

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No organization information available