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A real-time edge SAR imaging acceleration architecture utilizing multi-level dataflow parallelism
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DOI：10.1016/j.sysarc.2025.103635.png)
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Abstract
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• Propose a reconfigurable hardware architecture that integrates customized processing elements optimized for SAR. • Propose a multi-level dataflow model that exploits parallelism at the task, instruction, and node levels. • Present an instruction switching mechanism and a preprocessing method for matrix transposition to optimize the kernel switching overhead. • Demonstrates superior performance over CPU, GPU and other state-of-the-art methods through experiments on a representative SAR imaging algorithm.
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