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A sampled-data differentiator for time-mode signal processing
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DOI：10.1016/j.aeue.2026.156555.png)
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Abstract
En 中文
In this work, a sampled-data differentiator topology suitable for synchronous time-mode signal processing is proposed. The operation principle is based on the time-mode approach and the information is represented as the pulse width of rectangular pulses. The proposed topology uses a charge-based time register as a core circuit in order to implement unit delay tap and adder. Thanks to its modular, clock-synchronous structure, the differentiator can serve as building block in more complex time-mode systems. It is designed in TSMC 65 nm technology node, with 5 MS/s sampling rate. The power consumption is 137 mu W under 1.2 V voltage supply. Magnitude and phase frequency post-layout simulation responses match the corresponding response of an ideal delayed discrete-time differentiator.
Keywords:
Discrete-time signal processing
Time-mode PWM
Differentiator
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