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A sampling-based acceleration method for heterogeneous chiplet NoC simulations
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DOI：10.1016/j.future.2024.107643.png)
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Abstract
En 中文
To tackle the challenges posed by Moore's Law, Chiplet technology emerges as a promising solution. Chiplets comprising CPUs and accelerators are connected by Networks-on-Chip (NoC) for large-scale integration and efficient communications. However, the slow simulation speed of NoCs has become a bottleneck, limiting the overall performance of chiplet simulations. Existing solutions only focus on accelerating NoC simulation in homogeneous architecture. In this paper, we introduce a novel TOPSIS-based Heterogeneous Trace Score- sampling method (THTS) for faster NoC simulation in heterogeneous architecture. THTS enables quick and accurate sampling of representative NoC traces. Additionally, we propose a weight exploration model to further enhance sampling accuracy. Compared with the traditional NoC sampling method (NoCLabs), THTS reduces the error of the average packet latency by 22.17% and the total simulation time by 1.6 folds. THTS estimates the NoC performance with an average loss less than 5%, while speeding up the NoC simulation by up to 3 times. In addition, under different weight space sizes, the time required for the weight exploration model to solve the optimal weight vector is within seconds, remarkably speeding up the solution process. Notably, the predicted NoC simulation error under the optimal weight is only 1.42%.
Keywords:
Chiplet
Heterogeneous architecture
Network on chip
Sampling method
Simulation acceleration
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