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A Scalable Sorting Network Based on Hybrid Algorithms for Accelerating Data Sorting
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DOI：10.3390/electronics14030579.png)
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Abstract
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Sorting in sequential data mining is significantly improved through hardware acceleration, which becomes essential as data volume and complexity increase. This paper presents a scalable hybrid sorting network that maintains or improves performance while reducing computational load and hardware requirements. The network is composed of the pre-comparison odd-even sorting network (P-OESN) and the bidirectional insertion sorting network (BISN). A pre-comparison layer is introduced to the original OESN. This layer aims to place larger values in the first half of the input sequence and smaller values in the latter half. The number of iterations is reduced when the P-OESN transitions from fully parallel execution to iterative execution. A novel pipelined BISN architecture is proposed, which leads to enhanced operating frequency and throughput. The experimental results show that the pre-comparison layer reduces the number of iterations by 6% to 50%. Throughput is improved by more than four times, and operating frequency is increased by more than two times due to the pipelined BISN. The proposed hybrid sorting network reduces sorting time or resource usage, while enabling the sorting of large-scale data sets that other methods cannot support.
Keywords:
field programmable gate array (FPGA)
hybrid sorting network
scalable architecture
bidirectional processing
pre-comparison
pipeline technology
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