.png){kind=icon}
.png){kind=icon}
Return
A Serial Optical Link Based Memory Test System for High-Speed and Multi-Parallel Test
.png){kind=icon}
PRE
AI
DOI：10.1109/JLT.2009.2032788.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
A novel memory optical test solution is proposed and experimentally evaluated for at-speed DDR2-SDRAM test using a commercial automatic test equipment (ATE). Combination of an optical signal splitting scheme and SerDes (Serializer/De-Serializer) technique based on FPGA (Field programmable gate array) allows the high-speed multi-parallel memory test with reduced channel resources. Owing to the SerDes, optical fiber channels are reduced by more than 87 percent and the number of optical modules including transmitter/receiver dramatically decrease to 95 percent, compared with a conventional optical test interface system. Furthermore, the proposed system can optically expand the tester resource by 4 times using a 1 4 optical splitting scheme. We evaluated the signal integrity of 28 layer PCB operating at 3.125 Gbps with three-dimension electromagnetic simulation to obtain more reliable system for memory testing. Consequently, for the first time to the best of our knowledge, we realized an optical SerDes interconnect system for a memory test tester and demonstrated an actual write/read function test of DDR2-SDRAM.
Keywords:
Field programmable gate array (FPGA)
memory test
optical transmitter/receiver
SerDes (serializer/deserializer)
Journal
IF:
4.8
Papers:
1.7W
Citations:
3.8W