.png){kind=icon}
.png){kind=icon}
Return
A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSI.2011.2131370.png)
.png){kind=icon}
Original request for help.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 22 proof-of-concept array has been manufactured in 0.35 mu m CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low- and medium-level image processing on the chip are presented.
Keywords:
Asynchronous image processing
cellular processor array
smart sensor
vision chip
Journal
IF:
5.2
Papers:
9.7K
Citations:
2.2W