A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

doi:10.1109/JETCAS.2023.3243135

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

2023-03-01

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DOI：10.1109/JETCAS.2023.3243135

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Low-voltage computing effectively saves energy in circuit operations, but it suffers from an increasing propagation delay. Approximate computing can significantly reduce the propagation delay by using a simplified or improved circuit, albeit with an inevitable accuracy loss. To address these challenges, a timing-aware configurable adder (TACA) is proposed to achieve a good trade-off between energy efficiency and accuracy at low operating voltages. This design relies on the functions of timing-error detection and correction (TEDC) for the newly-proposed accuracy-configurable full adders (ACFAs). The ACFA operates in an exact mode and two approximate modes by using four transistors as power gating. The TEDC generates timing-error signals when the delay violates the timing constraint due to voltage overscaling. Then, an improved configuration scheme is developed to enable the ACFA to work in an approximate mode by allowing for error signals at runtime. This approximation shortens the carry propagation chain. Thus, the TACA is adapted to timing conditions at different supply voltages by reducing the propagation delay rather than the operation frequency.

Keywords:

Adders

Delays

Transistors

Energy efficiency

Logic gates

Propagation delay

Low voltage

Low-voltage operation

timing detection and correction

approximate computing

dynamic accuracy-configurable adder

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

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