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A Timing-Based Split-Path Sensing Circuit for STT-MRAM
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DOI：10.3390/mi13071004.png)
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Abstract
En 中文
Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (V-DD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal V-DD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75x sensing time.
Keywords:
dynamic reference voltage
read disturbance
read yield
sense amplifier
sensing circuit
spin-transfer torque magnetoresistive random access memory (STT-MRAM)
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