A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

doi:10.1109/TCSII.2023.3253707

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

2023-08-01

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DOI：10.1109/TCSII.2023.3253707

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This brief presents a two-phase multi-bit incremental analog-to-digital converter (IADC) with variable loop order. In the 1(st) phase, the loop filter works as a 1(st)-order topology. In the 2(nd) phase, the loop reconfigures to a 3(rd)-order structure, aiming to get the signal-to-quantization-noise ratio (SQNR) boosted quickly within a few clock cycles. Such a two-phase scheme with variable loop-order combines the features of the KT/C noise suppression and high effectiveness of data weighting averaging (DWA) presented by the 1(st)-order IADC and fast accumulation obtained from the high-order mode. Thereby, with little additional circuitry effort, the proposed IADC improves DWA effectiveness while mitigating the thermal noise penalty when compared with a pure high-order IADC. The proposed architecture is analytically analyzed and exemplarily simulated. Moreover, a design guideline is provided to optimize the allocation of the clock cycles of two phases, thus balancing various significant parameters. Based on the guideline, a circuit-level simulation of an exemplary 1(st)-to-3(rd) order IADC was carried out in a 65-nm CMOS process to confirm the results.

Keywords:

Incremental ADC

variable loop order

multi-bit quantizer

DWA effectiveness

noise penalty

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

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