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A Two-Step Processing in CMOS Image Sensor Architecture
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DOI：10.1109/JSEN.2025.3577057.png)
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Abstract
En 中文
The processing-in-sensor (PIS) architecture, which shifts computing capabilities to the sensing end, is proposed to address the communication bottleneck encountered when transmitting data from CMOS image sensors (CISs) to terminal hosts. Existing solutions often suffer from high structural complexity and insufficient computing speeds, negatively impacting overall performance. In this work, we introduce a PIS architecture that uses two-step computing technology to streamline circuit design, thereby accelerating the sensing-computing process. The simplified architecture also results in significant reductions in power consumption, leading to enhanced computational efficiency. Simulation results demonstrate that our proposed architecture achieves an efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${4.29}~\text {TOPS/W}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${60}~\text {frames/s}$ </tex-math></inline-formula>. Furthermore, we conducted an object detection task using the proposed PIS with a computer terminal, attaining a mean average precision (mAP) of 0.42, thus highlighting the effectiveness of our approach.
Keywords:
CMOS image sensor (CIS)
convolutional neural network (CNN)
feature extraction
processing-in-sensor (PIS)