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A write buffer design based on stable and area-saving embedded SRAM for flash applications
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DOI：10.1007/s11431-014-5725-8.png)
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Abstract
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This paper presents an embedded SRAM design for write buffer applications in flash memories. The write buffer is implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6 T SRAM cell units. A 2 kb SRAM macro with the area of 135 mu m x180 pm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process. Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.
Keywords:
write buffer
embedded SRAM
flash
65 nm technology
2 kb
128 Mb
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