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A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors
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DOI：10.1109/ACCESS.2022.3198989.png)
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Abstract
En 中文
Protecting cache memories against radiation-induced soft errors is critical in designing highly reliable processors. Dirty lines in write-back data caches are more critical, since the dirty lines have no backups in lower-level memory (LLM). This paper provides a write-buffer scheme for backing up dirty lines to protect cache memories based on the replication mechanism combined with interleaving parity check against multiple-bit errors. The write-buffer contains two same replication caches to replicate the dirty data from the original cache, and the two replication caches take turns to write the replicated data back to LLM during the free time when there is no access in LLM. In this way, the dirty data in original cache is backed up to LLM that can be used for error recovery, and meanwhile, spaces of the replication caches are released to replicate new dirty data; moreover, the writebacks of the replicated data can be performed in the background without extra clocks. Simulation results show that the proposed write-buffer scheme can provide a full protection for caches without degrading system performance, while it can improve the system performance by an average of 1.4% due to the background writebacks, and compared with state-of-the-art replication-based technique, it can increase the replication capability by 11.6% and save 6.2% energy consumption in case of the optimal configuration. It is superior to the existing techniques in terms of protection capability and system performance overhead.
Keywords:
Arrays
Program processors
Error correction codes
System performance
Parity check codes
Delays
Cache memory
Soft error
reliability
parity check
write-buffer
cache