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Accelerating memory and I/O intensive HPC applications using hardware compression
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DOI：10.1016/j.jpdc.2024.104955.png)
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Abstract
En 中文
Recently, accelerator-based compression/decompression was proposed to hide the storage latency of highperformance computing (HPC) applications that generate/ingest large data that cannot fit a node's memory. In this work, such a scheme has been implemented using a novel FPGA-based lossy compression/decompression scheme that has very low-latency. The proposed scheme completely overlaps the movement of the application's data with its compute kernels on the CPU with minimal impact on these kernels. Experiments showed that it can yield performance levels on-par with utilizing memory-only storage buffers, even though data is actually stored on disk. Experiments also showed that compared to CPU- and GPU-based compression frameworks, it achieves better performance levels at a fraction of the power consumption.
Keywords:
High performance computing
Reconfigurable computing
FPGA accelerators
Data compression
Memory intensive applications
Hardware co-design
Journal
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4
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3.8K
Citations:
4.8K
